Welcome!
[Sign In]
!
[Sign Up]
!
Front-page it
|
Collect it
| [
中国-简体中文
]
CodeBus
codebus.net
Hot search:
Source
embeded
web
remote control
p2p
game
More...
FAQ
Fav
Home
SourceCode
Web Code
Develop Tools
Document
E-Books
Other Resource
Get Coins
Member
Location:
Downloads
SourceCode
Embeded-SCM Develop
VHDL-FPGA-Verilog
Title:
ENCODE
Download
Category:
VHDL-FPGA-Verilog
Tags:
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
yinglun_007
Description:
Interleaved Coded achieve this source, source code for VHDL language. Running on the transmitter FPGA.
Downloaders recently:
[
More information of uploader yinglun_007
]
To Search:
[
SimulationinOFDM
] - OFDM simulation using Matlab, including
[
turbodecode
] - err
[
turbo[1].Tar
] - turbo code verilog procedures Interested
[
vhdl_crc
] - Quartus VHDL language used in the develo
[
TurboCode(c)
] - turbo code of the relevant procedures, c
[
MIPS
] - Composition Principle big operation- bas
[
flash_controller
] - Altera
[
interleaver
] - This is a convolutional interleaver code
[
interleaver
] - This is a prepared using VHDL interleave
[
DVB
] - DVB system, the reconciliation Interleav
File list
(Check if you may need any files):
ENCODE.vhd
Main Category
SourceCode
Web Code
Develop Tools
Document
Other resource
Category
About site
Total codes:
120
M
Total size:
1500
GB
Today updated:368
Members:1688565
Today members:634
Total members:198568
Downloaded:1200M
Sign UP
Help
Support
What's CodeBus
SiteMap
Contact us
CodeBus www.codebus.net
“CodeBus” is the largest source code store in internet!
1999-2018
CodeBus
All Rights Reserved.