Description: The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit configuration data automatically shift output, input clock 24MHz, resulting 1MHz clock configuration. 8-bit CPU data bus interface, address bus 11. IO-bit support for the home clearance.
- [EPPTOP] - epp model of parallel in fpga
- [LPT] - controling LED via parallel port
File list (Check if you may need any files):
LPT.vhd
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