Description: 32 slot of the VHDL source code in the development of E1 2M lines is very useful when
- [huawei] - Huawei FPGA design flow guide, FPGA desi
- [rpr] - Welcome everyone to download the learnin
- [Y312448] - VHDL based on the SDH ASIC Design TOP-DO
- [SDH] - Visual C++ Development environment is a
- [HardwareUDP] - Hardware UDP, implementation of UDP base
- [machester_VHDL] - manchester code in the communications ar
- [DNW0.50A] - The source code for the VC through USB t
- [sdh] - From the SDH data stream to find the cor
- [shift] - E1 to receive some of the major function
- [E1] - In the International Standards Organizat
File list (Check if you may need any files):
32时隙分割源代码.txt