Description: vga video outputs [vhdl], mainly arising from the SDRAM graphics, output to vga Medium
- [VGA_Core] - write VHDL VGA core, is a very good subs
- [vgacolor] - vga programming. Realization of the thre
- [VBuffer.1.1] - Video capture, store, send the Verilog s
- [vga] - VGA source code written in VHDL can be u
- [vga] - In cyclone2 chip VGA solutions, Analog O
- [FPGA-VGA-interface] - FPGA-based interface VGA display program
- [H264] - Under the latest h.264 standard c langua
- [edk_for_busy_people] - EDK document by Xilinx. EDK is used to b
- [HTCCamera] - DoPod official VGA camera bottom-driven,
- [VGALCD.ZIP] - vga lcd controller, writen by verilog
File list (Check if you may need any files):
Readme.txt
vga_vhdl_code
.............\ASCII2VGA
.............\.........\afficheur_7segments.vhd
.............\.........\afficheur_vga.vhdl
.............\.........\constraint.ucf
.............\.........\screen_memory.vhd
.............\.........\symbols_table.vhd
.............\.........\top.vhdl
.............\SDRAM_VGA_GEN
.............\.............\an-101204-vgagen
.............\.............\................\common.vhd
.............\.............\................\sdramcntl.vhd
.............\.............\................\vga-timing.xls
.............\.............\................\vga.vhd
.............\.............\................\xsasdramcntl.vhd
.............\vga
.............\...\vgatst
.............\...\......\LIB
.............\...\......\...\VGATST.BLK
.............\...\......\...\VGATST.DIR
.............\...\......\...\VGATST.FIG
.............\...\......\...\VGATST.FLG
.............\...\......\...\VGATST.GNR
.............\...\......\...\VGATST.HDR
.............\...\......\...\VGATST.ID
.............\...\......\...\VGATST.INI
.............\...\......\...\VGATST.MAP
.............\...\......\...\VGATST.MOD
.............\...\......\...\VGATST.PIN
.............\...\......\...\VGATST.SYM
.............\...\......\...\VGATST.SYN
.............\...\......\...\VGATST.VIS
.............\...\......\logiblox.ini
.............\...\......\vgacore.abl
.............\...\......\vgacore.bak
.............\...\......\vgatst.bit
.............\...\......\vgatst.prj
.............\...\......\vgatst.ucf
.............\...\......\vgatst1.SCH
.............\...\......\vgatst40.ucf
.............\...\......\vgatst95.ucf
.............\...\VGATST.PDF
.............\...\vgavhdl
.............\...\.......\express
.............\...\.......\.......\chips
.............\...\.......\.......\.....\vgacore
.............\...\.......\.......\.....\.......\vgacore.cst
.............\...\.......\.......\.....\.......\vgacore.rpt
.............\...\.......\.......\.....\.......\vgacore.trt
.............\...\.......\.......\.....\.......\vgacore.ws
.............\...\.......\.......\.....\vgacore-Optimized
.............\...\.......\.......\.....\.................\vgacore-Optimized.cst
.............\...\.......\.......\.....\.................\vgacore-Optimized.rpt
.............\...\.......\.......\.....\.................\vgacore-Optimized.trt
.............\...\.......\.......\.....\.................\vgacore-Optimized.ws
.............\...\.......\.......\express.exp
.............\...\.......\.......\files
.............\...\.......\.......\.....\L1.rpt
.............\...\.......\.......\workdirs
.............\...\.......\.......\........\WORK
.............\...\.......\.......\........\....\Anal.info
.............\...\.......\.......\........\....\Anal.out
.............\...\.......\.......\........\....\vgacore.hnl
.............\...\.......\.......\........\....\VGACORE.mra
.............\...\.......\.......\........\....\vgacore.out
.............\...\.......\.......\........\....\VGACORE.sim
.............\...\.......\.......\........\....\vgacore.sts
.............\...\.......\.......\........\....\VGACORE.syn
.............\...\.......\.......\........\....\VGACORE__VGACORE_ARCH.sim
.............\...\.......\.......\........\....\VGACORE__VGACORE_ARCH.syn
.............\...\.......\LIB
.............\...\.......\...\VGAVHDL.BLK
.............\...\.......\...\VGAVHDL.DIR
.............\...\.......\...\VGAVHDL.FIG
.............\...\.......\...\VGAVHDL.FLG
.............\...\.......\...\VGAVHDL.GNR
.............\...\.......\...\VGAVHDL.HDR
.............\...\.......\...\VGAVHDL.ID
.............\...\.......\...\VGAVHDL.INI
.............\...\.......\...\VGAVHDL.MAP
.............\...\.......\...\VGAVHDL.MOD
.............\...\.......\...\VGAVHDL.PIN
.............\...\.......\...\VGAVHDL.SYM
.............\...\.......\...\VGAVHDL.SYN
.............\...\.......\...\VGAVHDL.VIS
.............\...\.......\logiblox.ini
.............\...\.......\vgacore.bak
.............\...\.......\vgacore.vhd
.............\...\.......\vgacore.xnf
.............\...\.......\vgatst40.ucf
.............\...\......
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