Description: Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
- [cyclic] - FPGA serial communication program, accep
- [UART_VHDL] - Using VHDL language serial communication
- [EHERNETIPcore] - This document contains the relevant Ethe
- [ethernet_example] - FPGA to achieve the realization of Ether
- [FPGA_FIFO] - Prepared by the use of Verilog synchrono
- [UART] - Verilog prepared their own UART practica
- [uart] - FPGA-based multi-modem UART design, very
- [uart16550] - uart16550 is a 16550 compatible (mostly)
File list (Check if you may need any files):
uart8
.....\component
.....\.........\Actel
.....\.........\.....\DirectCore
.....\.........\.....\..........\COREUART
.....\.........\.....\..........\........\3.1.103
.....\.........\.....\..........\........\.......\coreparameters.v
.....\.........\.....\..........\........\.......\COREUART.cxf
.....\.........\.....\..........\........\.......\mti
.....\.........\.....\..........\........\.......\...\lib_vlog_obs
.....\.........\.....\..........\........\.......\...\............\COREUART_LIB
.....\.........\.....\..........\........\.......\...\............\............\_info
.....\.........\.....\..........\........\.......\...\scripts
.....\.........\.....\..........\........\.......\...\.......\wave_vlog.do
.....\.........\.....\..........\........\.......\rtl
.....\.........\.....\..........\........\.......\...\vlog
.....\.........\.....\..........\........\.......\...\....\core_obfuscated
.....\.........\.....\..........\........\.......\...\....\...............\Clock_gen.v
.....\.........\.....\..........\........\.......\...\....\...............\CoreUART.v
.....\.........\.....\..........\........\.......\...\....\...............\fifo_256x8_pa3.v
.....\.........\.....\..........\........\.......\...\....\...............\Rx_async.v
.....\.........\.....\..........\........\.......\...\....\...............\Tx_async.v
.....\.........\.....\..........\........\.......\...\....\test
.....\.........\.....\..........\........\.......\...\....\....\verif
.....\.........\.....\..........\........\.......\...\....\....\.....\testbnch.v
.....\.........\work
.....\.........\....\UartIP
.....\.........\....\......\testbench.v
.....\.........\....\......\UartIP.cxf
.....\.........\....\......\UartIP.sdb
.....\.........\....\......\UartIP.v
.....\constraint
.....\..........\uart_ctrl.sdc
.....\coreconsole
.....\...........\UartIP
.....\designer
.....\........\impl1
.....\........\.....\designer.log
.....\........\.....\designer_genhdl.log
.....\........\.....\PLL_1536.ide_des
.....\........\.....\PLL_33.ide_des
.....\........\.....\simulation
.....\........\.....\UartIP.ide_des
.....\........\.....\uart_control.ide_des
.....\........\.....\uart_ctrl.adb
.....\........\.....\uart_ctrl.dtf
.....\........\.....\.............\verify.log
.....\........\.....\uart_ctrl.ide_des
.....\........\.....\uart_ctrl.pdb
.....\........\.....\uart_ctrl.pdb.depends
.....\........\.....\uart_ctrl.stp
.....\........\.....\uart_ctrl.tcl
.....\........\.....\uart_ctrl_fp
.....\........\.....\............\$$FlashPro_08166.L$$
.....\........\.....\............\$$FlashPro_08424.L$$
.....\........\.....\............\projectData
.....\........\.....\............\...........\uart_ctrl.pdb
.....\........\.....\............\uart_ctrl.log
.....\........\.....\............\uart_ctrl.pro
.....\........\.....\uart_initial.ide_des
.....\hdl
.....\...\interface.v
.....\...\uart_control.v~RF14e5b17.TMP
.....\...\uart_control.v~RF1a74220.TMP
.....\...\uart_control.v~RF58c8e1.TMP
.....\...\uart_ctrl.v
.....\...\uart_ctrl.v.bak
.....\...\uart_ctrl.v~RF105819e.TMP
.....\...\uart_ctrl.v~RF17d802f.TMP
.....\...\uart_ctrl.v~RF1ec6b34.TMP
.....\...\uart_ctrl.v~RF275e2bb.TMP
.....\...\uart_initial.v
.....\...\uart_initial.v~RF1057e04.TMP
.....\phy_synthesis
.....\simulation
.....\..........\modelsim.ini
.....\..........\modelsim.ini.sav
.....\..........\modelsim.log
.....\..........\postsynth
.....\..........\.........\@c@o@r@e@u@a@r@t_0s_0s_15s
.....\..........\.........\..........................\verilog.psm
.....\..........\.........\..........................\_primary.dat
.....\..........\.........\..........................\_primary.dbs
.....\..........\.........\..........................\_primary.vhd
.....\..........\.........\@clock_gen
.....\..........\.........\..........\verilog.psm
.....\..........\.........\..........\_primary.dat
.....\..........\.........\..........\_primary.dbs
.....\..........\.........\..........\_primary.vhd
.....\..........\.........\@p@l@l_33
.....\..........\.........\.........\verilog.psm
.....\..........\.........\.........\_prim
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