Description: Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed hardware architecture, making the original 48 clock cycles required to complete the operation, and now only need one clock cycle can be completed. In addition by increasing the input/output control signal. Makes the IP can be easily integrated into the SOC, the SOC has significantly shortened the design cycle.
- [DES] - DES algorithm Verilog realized, the real
- [XAPP270] - High-Speed DES and Triple DES Encryptor
- [des3] - 3des encryption algorithm, after FPGA va
- [des] - this is des code of vhdl version.
- [DES_Encrypt_Decrypt_Verilog] - Des En/Decrypt,Verilog HDL code
File list (Check if you may need any files):
DES_IP
......\3des_log.txt
......\des3_top.v
......\des_cipher.v
......\des_key_sel.v
......\des_sbox1.v
......\des_sbox2.v
......\des_sbox3.v
......\des_sbox4.v
......\des_sbox5.v
......\des_sbox6.v
......\des_sbox7.v
......\des_sbox8.v
......\des_top.v
......\log.txt
......\tb_des.v
......\tb_des3.v
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