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Title: clock Download
 Description: Verilog implementation using digital stopwatch, download to FPGA development board to verify the adoption. After the download you can use the new distribution of pins.
 Downloaders recently: [More information of uploader lizhiqiangdx]
 To Search: verilog
File list (Check if you may need any files):
clock
.....\altpll0.bsf
.....\altpll0.ppf
.....\altpll0.v
.....\altpll0_bb.v

.....\altpll0_waveforms.html
.....\clock.asm.rpt
.....\clock.bdf
.....\clock.cdf
.....\clock.done
.....\clock.dpf
.....\clock.fit.rpt
.....\clock.fit.smsg
.....\clock.fit.summary
.....\clock.flow.rpt
.....\clock.map.rpt
.....\clock.map.smsg
.....\clock.map.summary
.....\clock.pin
.....\clock.pof
.....\clock.qpf
.....\clock.qsf
.....\clock.qws
.....\clock.sim.rpt
.....\clock.sof
.....\clock.tan.rpt
.....\clock.tan.summary
.....\clock.vwf
.....\clockdivisor.bsf
.....\clockdivisor.v
.....\clockdivisor.v.bak
.....\clock_description.txt
.....\db
.....\..\clock.asm.qmsg
.....\..\clock.asm_labs.ddb
.....\..\clock.atom.rvd
.....\..\clock.cbx.xml
.....\..\clock.cmp.bpm
.....\..\clock.cmp.cdb
.....\..\clock.cmp.ecobp
.....\..\clock.cmp.hdb
.....\..\clock.cmp.logdb
.....\..\clock.cmp.qrpt
.....\..\clock.cmp.rdb
.....\..\clock.cmp.tdb
.....\..\clock.cmp0.ddb
.....\..\clock.cmp_bb.cdb
.....\..\clock.cmp_bb.hdb
.....\..\clock.cmp_bb.logdb
.....\..\clock.cmp_bb.rcf
.....\..\clock.dbp
.....\..\clock.db_info
.....\..\clock.eco.cdb
.....\..\clock.eds_overflow
.....\..\clock.fit.qmsg
.....\..\clock.fnsim.hdb
.....\..\clock.fnsim.qmsg
.....\..\clock.hier_info
.....\..\clock.hif
.....\..\clock.map.bpm
.....\..\clock.map.cdb
.....\..\clock.map.ecobp
.....\..\clock.map.hdb
.....\..\clock.map.logdb
.....\..\clock.map.qmsg
.....\..\clock.map_bb.cdb
.....\..\clock.map_bb.hdb
.....\..\clock.map_bb.logdb
.....\..\clock.merge_hb.atm
.....\..\clock.pre_map.cdb
.....\..\clock.pre_map.hdb
.....\..\clock.psp
.....\..\clock.pss
.....\..\clock.rpp.qmsg
.....\..\clock.rtlv.hdb
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.sgate.rvd
.....\..\clock.sgate_sm.rvd
.....\..\clock.sgdiff.cdb
.....\..\clock.sgdiff.hdb
.....\..\clock.signalprobe.cdb
.....\..\clock.sim.cvwf
.....\..\clock.sim.hdb
.....\..\clock.sim.qmsg
.....\..\clock.sim.rdb
.....\..\clock.simfam
.....\..\clock.sld_design_entry.sci
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.syn_hier_info
.....\..\clock.tan.qmsg
.....\..\clock.tis_db_list.ddb
.....\..\prev_cmp_clock.asm.qmsg
.....\..\prev_cmp_clock.fit.qmsg
.....\..\prev_cmp_clock.map.qmsg
.....\..\prev_cmp_clock.qmsg
.....\..\prev_cmp_clock.sim.qmsg
.....\..\prev_cmp_clock.tan.qmsg
.....\..\wed.wsf
    

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