Description: Containing various types of registers, AD and DA converters, a variety of algorithms, finite state machine, but also some combinational logic circuit design code
- [TLC7524] - The program is implemented with VHDL lan
- [fpgafft] - FPGA dsp realize using the fft algorithm
- [50vvoltmeter] - Through an external keyboard to the syst
- [32divider] - 32-bit binary divider 2
- [MAX038SigPrj] - Their own procedures for MAX038 signal g
- [fpgaandveriloghdl] - FPGA in the embedded high-class coursewa
- [tlc5628VHDL] - vhdl counter tlc5628
- [AD] - FPGA control module of the AD7321 is per
- [dac] - Digital to Analog Converter code VHDL
File list (Check if you may need any files):
adder
.....\adder.ise
.....\adder.ise_ISE_Backup
.....\adder.ntrc_log
.....\adder.ut
.....\adder.vhd
.....\adder_cs.cel
.....\adder_cs.ucf
.....\adder_prev_built.ngd
.....\adder_summary.html
.....\_xmsgs
adder_cs
........\adder_cs.ise
........\adder_cs.ise_ISE_Backup
........\adder_cs.ntrc_log
........\adder_cs.ucf
........\adder_CS.ut
........\adder_CS.vhd
........\adder_CS_summary.html
........\iscas.vhd
........\test.vhd
........\test_PK.vhd
count
.....\core_counnt.asy
.....\core_counnt.edn
.....\core_counnt.sym
.....\core_counnt.v
.....\core_counnt.veo
.....\core_counnt.vhd
.....\core_counnt.vho
.....\core_counnt.xco
.....\core_counnt_flist.txt
.....\core_count.xco
.....\count.ise
.....\count.ise_ISE_Backup
.....\count.ntrc_log
.....\counter.ucf
.....\counter.ut
.....\counter.vhd
.....\counter_summary.html
.....\templates
.....\.........\coregen.xml
.....\test.xco
.....\vga_16.vhd
.....\_cg
.....\_xmsgs
.....\__ISE_repository_count.ise_.lock
counter
.......\counter.ise
.......\counter.ise_ISE_Backup
.......\counter.ntrc_log
.......\counter.vhd
.......\count_sim.jhd
.......\count_sim.tbw
.......\count_sim.tbw.bak
.......\count_sim.tbw_trans
.......\count_top.ut
.......\count_top.vhd
.......\count_top_summary.html
.......\HEX2LED_4.vhd
.......\vga_16.vhd
.......\work
.......\....\count
.......\....\.....\behavioral.asm
.......\....\.....\behavioral.dat
.......\....\.....\_primary.dat
.......\....\counter
.......\....\.......\behavioral.asm
.......\....\.......\behavioral.dat
.......\....\.......\_primary.dat
.......\....\counter_cfg
.......\....\...........\_primary.dat
.......\....\...........\_vhdl.asm
.......\....\count_sim
.......\....\.........\testbench_arch.asm
.......\....\.........\testbench_arch.dat
.......\....\.........\_primary.dat
.......\....\_info
.......\_cg
.......\...\_cg_exc.out
.......\_xmsgs
.......\__ISE_repository_counter.ise_.lock
counter_core
............\counter.asy
............\counter.edn
............\counter.sym
............\counter.ucf
............\counter.v
............\counter.veo
............\counter.vhd
............\counter.vho
............\counter.xco
............\counter_core.ise
............\counter_core.ise_ISE_Backup
............\counter_core.npl
............\counter_core.npl_ISE_Backup
............\counter_core.ntrc_log
............\counter_flist.txt
............\count_top.ut
............\count_top.vhd
Download