- Category:
- MPI
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[Text]
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- 1kb
- Update:
- 2012-11-26
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- kimli
Description: SERDES VHDL source code, you can achieve signal at between serial and parallel conversion.
- [SPtransform] - Verilog HDL Series and the preparation o
- [5] - String and the conversion process, from
- [uart] - Strings parallel to achieve communicatio
- [apb_bridge] - arm ambm 2.0 primecell algorithm ahb con
- [auk_sdsdi] - for FPGA design ,written by Verilog HDL
- [FPGA_common_idea] - This article discusses the four commonly
- [SONETSDH] - una aplicacion de sonet
- [timingrecoveryofdvb] - DVB System Based on QAM modulation clock
- [fjq3] - Presents a FPGA-based digital multiplexi
- [p_s] - Series with the Verilog HDL language and
File list (Check if you may need any files):
readme_vhd.txt