Description: for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
File list (Check if you may need any files):
auk_sdsdi-v1.1
..............\doc
..............\...\an356.pdf
..............\...\readme.txt
..............\quartus
..............\.......\sdsdi_rxtx_cyclone_board
..............\.......\........................\sdsdi_rxtx_cyclone_board.qpf
..............\.......\........................\sdsdi_rxtx_cyclone_board.qsf
..............\.......\sdsdi_rxtx_demoboard
..............\.......\....................\sclk_pll_x50_4.v
..............\.......\....................\sdsdi_rxtx_demoboard.qpf
..............\.......\....................\sdsdi_rxtx_demoboard.qsf
..............\simulate
..............\........\tb_sdsdi_rxtx
..............\........\.............\run.bat
..............\........\.............\wave.do
..............\source
..............\......\cyclone_board
..............\......\.............\sdsdi_rxtx_cyclone_board.v
..............\......\demo
..............\......\....\fifo_256x20.v
..............\......\....\freq_trans.v
..............\......\....\sclk_pll_x10.v
..............\......\....\sclk_pll_x30_4.v
..............\......\....\sclk_pll_x50_4.v
..............\......\....\sdsdi_io_interface.v
..............\......\....\sdsdi_rxtx.v
..............\......\....\sync.v
..............\......\demoboard
..............\......\.........\sdsdi_rxtx_demoboard.v
..............\......\sdi_receive
..............\......\...........\gxb_rxsample.v
..............\......\...........\s2p.v
..............\......\...........\sdi_aligner.v
..............\......\...........\sdi_descrambler.v
..............\......\...........\sdsdi_receive.v
..............\......\sdi_transmit
..............\......\............\gen_colorbar.v
..............\......\............\gen_patho.v
..............\......\............\p2s.v
..............\......\............\pattern_gen.v
..............\......\............\sdi_makeframe.v
..............\......\............\sdi_scrambler.v
..............\source_vhdl
..............\...........\cyclone_board
..............\...........\.............\sdsdi_rxtx_cyclone_board.vhd
..............\...........\demo
..............\...........\....\fifo_256x20.vhd
..............\...........\....\freq_trans.vhd
..............\...........\....\sclk_pll_x10.vhd
..............\...........\....\sclk_pll_x30_4.vhd
..............\...........\....\sclk_pll_x50_4.vhd
..............\...........\....\sdsdi_io_interface.vhd
..............\...........\....\sdsdi_rxtx.vhd
..............\...........\....\sync.vhd
..............\...........\demoboard
..............\...........\.........\sdsdi_rxtx_demoboard.vhd
..............\...........\lib
..............\...........\...\sdi_std_logic.vhd
..............\...........\sdi_receive
..............\...........\...........\gxb_rxsample.vhd
..............\...........\...........\s2p.vhd
..............\...........\...........\sdi_aligner.vhd
..............\...........\...........\sdi_descrambler.vhd
..............\...........\...........\sdsdi_receive.vhd
..............\...........\sdi_transmit
..............\...........\............\gen_colorbar.vhd
..............\...........\............\gen_patho.vhd
..............\...........\............\p2s.vhd
..............\...........\............\pattern_gen.vhd
..............\...........\............\sdi_makeframe.vhd
..............\...........\............\sdi_scrambler.vhd
..............\tb
..............\..\tb_sdsdi_rxtx.v
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