DDC Verilog language implementation of the digital

Title: DDC

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
43kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
wendy_cn

Description: Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.

Downloaders recently: [More information of uploader wendy_cn]

To Search: ddc verilog DDC VHDL Verilog ddc vhdl ddc verilog ddc veril Carrier Recovery veril DDC verilog verilog downconversi

[copyDPLLprocedures.Rar] - DPLL source with cpld prepared after the
[muxplusii--VHDLclassicprocedures.Rar] - prepared using VHDL digital clock, Varia
[jaguar2s] - 8-1024 points FFT/IFFT transform, VHDL d
[dpll0227] - DPLL simultaneously extract a certain ef
[tiaozhijietiao] - QPSK modulation and demodulation process
[testbench] - IC verification, a rare book, talking ab
[CordicNCO] - Based on the CORDIC algorithm, the digit
[DDC_polyphase] - An DDC program by myself
[1920X1080] - DIY a high-definition LCD TV 1920X1080 e
[can_bus] - C-bus program can achieve network node,

File list (Check if you may need any files):

DDC
...\acc32local.v
...\DDC.vhd
...\dds1.v
...\hex
...\...\cos_4096.hex
...\...\cos_4096.ver
...\...\sin_4096.hex
...\...\sin_4096.ver
...\muldown.v
...\rom_cos1.v
...\rom_sin1.v

Main Category

SourceCode

Web Code

Develop Tools

Document

Other resource

Category

About site

CodeBus www.codebus.net