Description: FPGA chips ADI' s AD9779 and communication between, a total of four channels, 68 pairs of LVDS, the sampling clock is 122.88MHz
- [Huaweiinternalinformation.Rar] - Huawei internal information, hardware en
- [fpga_design] - This is a how to efficiently prepare fpg
- [fpgapcicom] - PCI is a high-performance local bus stan
- [IP_SPI] - spi bus vhdl code Shileshi can use. The
- [datang(FPGA)] - Datang Telecom FPGA design experience. P
- [osc] - Digital Oscilloscope The FPGA realizatio
- [diff_io_top] - LVDS Application of Verilog HDL examples
- [USB] - Functions/Classes:
- [USB2.0+FPGA+DSP] - usb2.0+ fpga+ dsp development board sche
- [2] - FPGA design analysis of a few basic ques
File list (Check if you may need any files):
LVDS_DDR_List_FPGA2
...................\coregen.cgp
...................\CS.cdc
...................\DDR_TX.v
...................\ddr_tx_test.bgn
...................\ddr_tx_test.bit
...................\DDR_TX_TEST.bld
...................\DDR_TX_TEST.cmd_log
...................\ddr_tx_test.drc
...................\DDR_TX_TEST.ise
...................\DDR_TX_TEST.lso
...................\DDR_TX_TEST.ncd
...................\DDR_TX_TEST.ngc
...................\DDR_TX_TEST.ngd
...................\DDR_TX_TEST.ngr
...................\DDR_TX_TEST.ntrc_log
...................\DDR_TX_TEST.pad
...................\DDR_TX_TEST.par
...................\DDR_TX_TEST.pcf
...................\DDR_TX_TEST.prj
...................\DDR_TX_TEST.ptwx
...................\DDR_TX_TEST.restore
...................\DDR_TX_TEST.stx
...................\DDR_TX_TEST.syr
...................\DDR_TX_TEST.twr
...................\DDR_TX_TEST.twx
...................\DDR_TX_TEST.unroutes
...................\DDR_TX_TEST.ut
...................\DDR_TX_TEST.v
...................\DDR_TX_TEST.xpi
...................\DDR_TX_TEST.xst
...................\DDR_TX_TEST_guide.ncd
...................\DDR_TX_TEST_map.map
...................\DDR_TX_TEST_map.mrp
...................\DDR_TX_TEST_map.ncd
...................\DDR_TX_TEST_map.ngm
...................\DDR_TX_TEST_map.xrpt
...................\DDR_TX_TEST_ngdbuild.xrpt
...................\DDR_TX_TEST_pad.csv
...................\DDR_TX_TEST_pad.txt
...................\DDR_TX_TEST_par.xrpt
...................\DDR_TX_TEST_prev_built.ngd
...................\DDR_TX_TEST_summary.html
...................\DDR_TX_TEST_summary.xml
...................\DDR_TX_TEST_usage.xml
...................\DDR_TX_TEST_xdb
...................\...............\cst.xbcd
...................\...............\tmp
...................\...............\...\ise
...................\...............\...\...\version
...................\...............\...\...\__OBJSTORE__
...................\...............\...\...\............\Autonym
...................\...............\...\...\............\common
...................\...............\...\...\............\HierarchicalDesign
...................\...............\...\...\............\..................\HDProject
...................\...............\...\...\............\..................\.........\HDProject
...................\...............\...\...\............\..................\.........\HDProject_StrTbl
...................\...............\...\...\............\..................\__stored_object_table__
...................\...............\...\...\............\PnAutoRun
...................\...............\...\...\............\.........\Scripts
...................\...............\...\...\............\.........\.......\RunOnce_tcl
...................\...............\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...................\...............\...\...\............\ProjectNavigator
...................\...............\...\...\............\................\dpm_project_main
...................\...............\...\...\............\................\................\dpm_project_main
...................\...............\...\...\............\................\................\dpm_project_main_StrTbl
...................\...............\...\...\............\................\................\NameMap
...................\...............\...\...\............\................\................\NameMap_StrTbl
...................\...............\...\...\............\................\__stored_objects__
...................\...............\...\...\............\................\__stored_objects___StrTbl
...................\...............\...\...\............\................\__stored_object_table__
...................\...............\...\...\............\ProjectNavigatorGui
...................\...............\...\...\............\...................\GuiProjectData
...................\...............\...\...\............\...................\GuiProjectData_StrTbl
...................\...............\...\...\............\SrcCtrl
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