Mars_EP1C6F_Fundermental_demo(Verilog) FPGA develo

Title: Mars_EP1C6F_Fundermental_demo(Verilog)

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
1.19mb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
chenlu0806

Description: FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.

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File list (Check if you may need any files):

基础实验
........\8位优先编码器
........\.............\.xhdl3.xref
........\.............\cmp_state.ini
........\.............\db
........\.............\..\encode.asm.qmsg
........\.............\..\encode.cbx.xml
........\.............\..\encode.cmp.cdb
........\.............\..\encode.cmp.hdb
........\.............\..\encode.cmp.qrpt
........\.............\..\encode.cmp.rdb
........\.............\..\encode.cmp.tdb
........\.............\..\encode.cmp0.ddb
........\.............\..\encode.dbp
........\.............\..\encode.db_info
........\.............\..\encode.eco.cdb
........\.............\..\encode.fit.qmsg
........\.............\..\encode.hier_info
........\.............\..\encode.hif
........\.............\..\encode.map.cdb
........\.............\..\encode.map.hdb
........\.............\..\encode.map.qmsg
........\.............\..\encode.pre_map.cdb
........\.............\..\encode.pre_map.hdb
........\.............\..\encode.psp
........\.............\..\encode.rtlv.hdb
........\.............\..\encode.rtlv_sg.cdb
........\.............\..\encode.rtlv_sg_swap.cdb
........\.............\..\encode.sgdiff.cdb
........\.............\..\encode.sgdiff.hdb
........\.............\..\encode.signalprobe.cdb
........\.............\..\encode.sld_design_entry.sci
........\.............\..\encode.sld_design_entry_dsc.sci
........\.............\..\encode.syn_hier_info
........\.............\..\encode.tan.qmsg
........\.............\..\encode_cmp.qrpt
........\.............\encode.asm.rpt
........\.............\encode.cdf
........\.............\encode.done
........\.............\encode.fit.eqn
........\.............\encode.fit.rpt
........\.............\encode.fit.summary
........\.............\encode.flow.rpt
........\.............\encode.map.eqn
........\.............\encode.map.rpt
........\.............\encode.map.summary
........\.............\encode.pin
........\.............\encode.pof
........\.............\encode.qpf
........\.............\encode.qsf
........\.............\encode.qws
........\.............\encode.sof
........\.............\encode.tan.rpt
........\.............\encode.tan.summary
........\.............\encode.v
........\.............\encode.v.bak
........\.............\encode_assignment_defaults.qdf
........\乘法器
........\......\.xhdl3.xref
........\......\cmp_state.ini
........\......\db
........\......\..\mlt.asm.qmsg
........\......\..\mlt.cbx.xml
........\......\..\mlt.cmp.cdb
........\......\..\mlt.cmp.hdb
........\......\..\mlt.cmp.qrpt
........\......\..\mlt.cmp.rdb
........\......\..\mlt.cmp.tdb
........\......\..\mlt.cmp0.ddb
........\......\..\mlt.dbp
........\......\..\mlt.db_info
........\......\..\mlt.eco.cdb
........\......\..\mlt.fit.qmsg
........\......\..\mlt.hier_info
........\......\..\mlt.hif
........\......\..\mlt.map.cdb
........\......\..\mlt.map.hdb
........\......\..\mlt.map.qmsg
........\......\..\mlt.pre_map.cdb
........\......\..\mlt.pre_map.hdb
........\......\..\mlt.psp
........\......\..\mlt.rtlv.hdb
........\......\..\mlt.rtlv_sg.cdb
........\......\..\mlt.rtlv_sg_swap.cdb
........\......\..\mlt.sgdiff.cdb
........\......\..\mlt.sgdiff.hdb
........\......\..\mlt.signalprobe.cdb
........\......\..\mlt.sld_design_entry.sci
........\......\..\mlt.sld_design_entry_dsc.sci
........\......\..\mlt.syn_hier_info
........\......\..\mlt.tan.qmsg
........\......\..\mlt_cmp.qrpt
........\......\mlt.asm.rpt
........\......\mlt.done
........\......\mlt.fit.eqn
........\......\mlt.fit.rpt
........\......\mlt.fit.summary
........\......\mlt.flow.rpt
........\......\mlt.map.eqn
........\......\mlt.map.rpt

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