PROCESSOR
.........\bde.set
.........\Celoxica
.........\........\Verilog
.........\........\.......\processor_top.v
.........\........\.......\proc_hcc.v
.........\compilation.order
.........\compile
.........\.......\contents.lib~
.........\compile.cfg
.........\default_compile.do
.........\implement
.........\.........\ver1
.........\.........\....\rev1
.........\.........\....\....\simulation
.........\.........\....\....\..........\custom
.........\.........\....\....\..........\......\processor_top.vo
.........\.........\....\....\..........\......\processor_top_v.sdo
.........\library.cfg
.........\log
.........\...\console.log
.........\proc.hcc
.........\processor.adf
.........\processor.aws
.........\processor.hp
.........\processor.LIB
.........\processor.wsp
.........\processor.wsw
.........\processor_post_synthesis
.........\........................\processor_post_synthesis.LIB
.........\processor_timing
.........\................\processor_timing.LIB
.........\projlib.cfg
.........\src
.........\...\Celoxica
.........\...\........\readme.txt
.........\...\Cosim
.........\...\.....\processor_top_wrapper.v
.........\...\post-synthesis
.........\...\..............\readme.txt
.........\...\processor_top_TB.v
.........\...\processor_top_TB_cosim.do
.........\...\processor_top_TB_func.do
.........\...\processor_top_TB_synth.do
.........\...\processor_top_TB_tim.do
.........\...\readme.txt
.........\...\timing
.........\...\......\readme.txt
.........\synthesis
.........\.........\processor_top.vm
.........\.........\processor_top.vqm