SDRAM This is an FPGA-based controller system, the

Title: SDRAM

Category:
VHDL-FPGA-Verilog
Tags:
[ASM] [源码]
File Size:
2.07mb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
jyb6844

Description: This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing

Downloaders recently: [More information of uploader jyb6844]

To Search: sdram sdram vhdl

[rd1014] - SDRAM controller, SDRAM to write for pag
[SDRAMtest] - SDRAM read and write tests for our in-de
[DDR_SDRAM_DesignSummarize] - Based on the Xilinx Spartan family of de
[SDRAM] - SDRAM principle and timing, for the real
[SDRAM_simulation_model] - SDRAM testing procedures and to read and
[dsppart34] - From the partial fraction expansion of H
[TCPthread] - unix program of tcp ip client server for
[mem_ctrl_latest.tar] - FPGA memory control processes, including
[sdram-source] - source code from altera

File list (Check if you may need any files):

实战训练13 SDRAM读写控制的实现与Modelsim仿真
............................................\doc
............................................\...\micron_sdram.pdf
............................................\part1
............................................\.....\part1_32
............................................\.....\........\model
............................................\.....\........\.....\mt48lc2m32b2.v
............................................\.....\........\rtl
............................................\.....\........\...\Command.v
............................................\.....\........\...\control_interface.v
............................................\.....\........\...\Params.v
............................................\.....\........\...\sdr_data_path.v
............................................\.....\........\...\sdr_sdram.v
............................................\.....\........\sim
............................................\.....\........\...\Command.v
............................................\.....\........\...\control_interface.v
............................................\.....\........\...\mt48lc2m32b2.v
............................................\.....\........\...\Params.v
............................................\.....\........\...\sd32try.cr.mti
............................................\.....\........\...\sd32try.mpf
............................................\.....\........\...\sdram_test_tb.v
............................................\.....\........\...\sdr_data_path.v
............................................\.....\........\...\sdr_sdram.v
............................................\.....\........\...\sdtry.cr.mti
............................................\.....\........\...\vsim.wlf
............................................\.....\........\...\wave.do
............................................\.....\........\...\work
............................................\.....\........\...\....\command
............................................\.....\........\...\....\.......\verilog.asm
............................................\.....\........\...\....\.......\_primary.dat
............................................\.....\........\...\....\.......\_primary.vhd
............................................\.....\........\...\....\control_interface
............................................\.....\........\...\....\.................\verilog.asm
............................................\.....\........\...\....\.................\_primary.dat
............................................\.....\........\...\....\.................\_primary.vhd
............................................\.....\........\...\....\mt48lc2m32b2
............................................\.....\........\...\....\............\verilog.asm
............................................\.....\........\...\....\............\_primary.dat
............................................\.....\........\...\....\............\_primary.vhd
............................................\.....\........\...\....\sdram_test_tb
............................................\.....\........\...\....\.............\verilog.asm
............................................\.....\........\...\....\.............\_primary.dat
............................................\.....\........\...\....\.............\_primary.vhd
............................................\.....\........\...\....\sdr_data_path
............................................\.....\........\...\....\.............\verilog.asm
............................................\.....\........\...\....\.............\_primary.dat
............................................\.....\........\...\....\.............\_primary.vhd
............................................\.....\........\...\....\sdr_sdram
............................................\.....\........\...\....\.........\verilog.asm
............................................\.....\........\...\....\.........\_primary.dat
............................................\.....\........\...\....\..

Main Category

SourceCode

Web Code

Develop Tools

Document

Other resource

Category

About site

CodeBus www.codebus.net