Description: CNTR 4: will be conducted at 50MHz clock frequency as the clock after the control conditions to determine the basis of inputs, and then set up a four through the results of the vector output, digital display board in the experiment
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......\cmp_state.ini
......\daima.txt
......\db
......\..\stmch1.asm.qmsg
......\..\stmch1.cbx.xml
......\..\stmch1.cmp.cdb
......\..\stmch1.cmp.hdb
......\..\stmch1.cmp.logdb
......\..\stmch1.cmp.rdb
......\..\stmch1.cmp.tdb
......\..\stmch1.cmp0.ddb
......\..\stmch1.db_info
......\..\stmch1.eco.cdb
......\..\stmch1.eds_overflow
......\..\stmch1.fit.qmsg
......\..\stmch1.fnsim.cdb
......\..\stmch1.fnsim.hdb
......\..\stmch1.hier_info
......\..\stmch1.hif
......\..\stmch1.map.cdb
......\..\stmch1.map.hdb
......\..\stmch1.map.logdb
......\..\stmch1.map.qmsg
......\..\stmch1.pre_map.cdb
......\..\stmch1.pre_map.hdb
......\..\stmch1.psp
......\..\stmch1.rtlv.hdb
......\..\stmch1.rtlv_sg.cdb
......\..\stmch1.rtlv_sg_swap.cdb
......\..\stmch1.sgdiff.cdb
......\..\stmch1.sgdiff.hdb
......\..\stmch1.signalprobe.cdb
......\..\stmch1.sim.hdb
......\..\stmch1.sim.qmsg
......\..\stmch1.sim.rdb
......\..\stmch1.sim.vwf
......\..\stmch1.sld_design_entry.sci
......\..\stmch1.sld_design_entry_dsc.sci
......\..\stmch1.smp_dump.txt
......\..\stmch1.syn_hier_info
......\..\stmch1.tan.qmsg
......\..\stmch1_cmp.qrpt
......\..\stmch1_sim.qrpt
......\my2.txt
......\stmch1.asm.rpt
......\stmch1.done
......\stmch1.fit.eqn
......\stmch1.fit.rpt
......\stmch1.fit.summary
......\stmch1.flow.rpt
......\stmch1.map.eqn
......\stmch1.map.rpt
......\stmch1.map.summary
......\stmch1.pin
......\stmch1.qpf
......\stmch1.qsf
......\stmch1.qws
......\stmch1.sim.rpt
......\stmch1.tan.rpt
......\stmch1.tan.summary
......\stmch1.vhd
......\stmch1.vwf
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