Description: DDS generator NIOS. C files, NIOSII can be in Verilog code generation with custom peripherals DDS generated signal
- [VHDL] - VHDL digital clock digital electronic cl
- [DE2_SD_Card_Audio] - NIOSII, on the MP3 source code, using SO
- [embeddeddevelop] - embedded linux embedded system design-dr
- [fxsf] - I collect things that do not have Vb, an
- [Altera] - The use of soft-core processor, Nios Ⅱ t
- [NIOS] - Nios cited frequently used functions, as
- [dual_ram] - FPGA and dual-port RAM of the DDS Arbitr
- [vhld_fpga_box] - Prepared Verilog waveform generator, can
- [QIMO] - Verilog prepared arbitrary waveform gene
File list (Check if you may need any files):