Description: Prepared Verilog waveform generator, can occur sine, triangle wave, square wave, you can FM
- [FPGA--DDS-PhaseMeasure] - Verilog realize the DDS sine wave signal
- [sine] - Verilog language prepared by the sine wa
- [signal] - VHDL-based multi-language source wavefor
- [verilog_sin_complete] - Verilog design module sinusoidal wavefor
- [MCAS_Code] - With C# Write the USB data acquisition p
- [dds] - FPGA realization of the use of DDS, sine
- [dds_drive.c] - DDS generator NIOS. C files, NIOSII can
- [vhdl] - VHDL language using FPGA-based waveform
- [wavegenerator] - Development environment for QuartusII, c
- [learn_dds] - Quartus ii 9.0 Based on dds simple wavef
File list (Check if you may need any files):
用vhdl语言编写的基于FPGA的波形发生器
....................................\box
....................................\...\allwave.mif
....................................\...\allwave.vhd
....................................\...\BOX.asm.rpt
....................................\...\BOX.cdf
....................................\...\BOX.done
....................................\...\BOX.fit.eqn
....................................\...\BOX.fit.rpt
....................................\...\BOX.fit.summary
....................................\...\BOX.flow.rpt
....................................\...\BOX.map.eqn
....................................\...\BOX.map.rpt
....................................\...\BOX.map.summary
....................................\...\BOX.pin
....................................\...\BOX.pof
....................................\...\BOX.qpf
....................................\...\BOX.qsf
....................................\...\BOX.qws
....................................\...\BOX.sim.rpt
....................................\...\BOX.sof
....................................\...\BOX.tan.rpt
....................................\...\BOX.tan.summary
....................................\...\BOX.vhd
....................................\...\BOX.vwf
....................................\...\BOX_assignment_defaults.qdf
....................................\...\db
....................................\...\..\add_sub_4rh.tdf
....................................\...\..\add_sub_5rh.tdf
....................................\...\..\add_sub_8rh.tdf
....................................\...\..\add_sub_ish.tdf
....................................\...\..\altsyncram_dpu.tdf
....................................\...\..\altsyncram_sfa2.tdf
....................................\...\..\altsyncram_tjb2.tdf
....................................\...\..\BOX.db_info
....................................\...\..\BOX.eco.cdb
....................................\...\..\BOX.sld_design_entry.sci
....................................\...\..\cmpr_fnh.tdf
....................................\...\..\cntr_0id.tdf
....................................\...\..\cntr_mbb.tdf
....................................\...\..\cntr_tia.tdf
....................................\...\..\cntr_ulb.tdf
....................................\...\..\cntr_vcc.tdf
....................................\...\..\decode_9ie.tdf
....................................\...\..\mux_8ec.tdf
....................................\...\..\mux_ecc.tdf
....................................\...\..\mux_qfc.tdf
....................................\...\..\wed.wsf
....................................\...\PLLU.cmp
....................................\...\PLLU.vhd
....................................\...\stp1.stp
....................................\使用说明请参看右侧注释====〉〉.txt
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