Description: I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
- [asinewavegeneratorandthewaveformgenerator.] - This is a typical wave generator Shogen
- [DDS_sin] - VHDL DDS Direct Digital Frequency Synthe
- [dds_8bit] - rom address the width of 8, 256 sine wav
- [DDS] - In FPGA-based lookup table approach (LUT
- [rom] - A 16 × 8bit the ROM initialization proce
- [ram_da] - AD conversion will be the eight data int
- [ddswase] - dds signal generator, can generate any f
- [testrom_1] - EDA experimental ROM experiment: the use
- [CPUVHDL] - CPU+ VHDL code and detailed notes \ a fo
- [DDS] - Our group for a month to do a total of D
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