Description: In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualco
- [CORDIC_mixer] - FPGA can be achieved, the use of the NCO
- [tdmddc_v71] - ddc the VHDL source code, no debugging,
- [uwb_syn] - Synchronization module with UWB simulati
- [matlab_simulink_basic_book] - Very classic MATLAB/SIMULINK entry books
- [ISE_chinese] - Xilinx ISE Chinese Concise Guide, Xilinx
- [DDS] - DDS frequency conversion can be consider
- [ddc] - Digital Down Converter for matlab realiz
- [test_uart] - uart VHDL code : include tx,rx,parity bi
- [DDS] - this is a code for DDS in Verilog
- [ZigBeeFpga] - Standards-based ZigBee wireless transcei
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