Description: Using VHDL description Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
- [rtl_DRAM] - program for the use of the Verilog langu
- [ram] - RAM prepared VHDL example
- [dram_control] - Using VHDL description Universal Asynchr
- [lfsr] - Pseudo-random sequence generator- linear
- [USB2.0IP] - Complete Verilog language developed by U
- [decode] - LDPC of Verilog source code, including t
- [dram_cntl] - DRAM Controller verilog file
- [sdram32] - DDR SDRAM source verilog source codes
File list (Check if you may need any files):
dram_controller.vhd
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