Description: FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.
To Search:
- [ep1c20] - Alterla official version ep1c20 NOISII F
- [USB2.0] - usb+ fpga development board schematics,
- [Uart_Send] - UART to send the complete procedure, inc
- [Vim7_2_manue.pdf] - Vim latest English manual, learning vi e
- [SSCOM-SPt] - 8 characteristics: 1. Automatically enum
- [ALTERA] - 5 ALTERA FPGA development board schemati
- [sdram_hr_hw] - In FPGA hardware realize computer data t
File list (Check if you may need any files):
第六章
......\adder8_for
......\..........\adder8_for.v
......\..........\adder8_for_tb.tf
......\BCDadder4
......\.........\adder4.v
......\.........\BCDadder4.v
......\.........\BCDadder4_tb.tf
......\bin2gra
......\.......\bin2gra.v
......\.......\bin2gra_tb.tf
......\cnt99
......\.....\cnt99_tb.tf
......\.....\cnt_10.V
......\.....\counter.V
......\comp4_if
......\........\comp4_if.v
......\........\comp4_if_tb.tf
......\counter_sim
......\...........\counter_sim.v
......\...........\counter_simtb.tf
......\count_0s
......\........\count_0s.v
......\demul1_4_if
......\...........\demul1_4_if.v
......\...........\demul1_4_if_tb.tf
......\encod8_3_casez
......\..............\encod8_3_casex.v
......\..............\encod8_3_casex_tb.tf
......\first_0
......\.......\first_0.v
......\.......\first_0_tb.tf
......\gra2bin
......\.......\gra2bin.v
......\.......\gra2bin_tb.tf
......\latch4_if
......\.........\latch4_if.v
......\mul3_1_casez
......\............\mul3_1_casez.v
......\............\mul3_1_casz_tb.tf
......\mul4_1_case
......\...........\mul4_1_case.v
......\...........\mul4_1_case_tb.tf
......\mul4_1_if
......\.........\mul4_1_if.v
......\.........\mul4_1_if_tb.tf
......\mul4_2_1
......\........\mul4_2_1.v
......\........\mut4_2_1tb.tf
......\RAM16x8d
......\........\RAM16x8d.v
......\........\RAM16x8d_tb.tf
......\RAM16x8sng
......\..........\RAM16x8sng.v
......\..........\RAM16x8sng_tb.tf
......\reg4_bpa
......\........\reg4_bpa.v
......\........\reg4_bpa_tb.tf
......\reg4_nbp
......\........\reg4_nbp.v
......\........\reg4_nbp_tb.tf
......\repeat_1s
......\.........\repeat_1s.v
......\.........\repeat_tb.tf
......\sevenseg_case
......\.............\sevenseg_case.v
......\.............\sevenseg_case_tb.tf
......\shl4_for
......\........\shl4_for.v
......\........\shl4_for_tb.tf
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