Description: The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment using different occasions 3. Test the preparation of learning modules, integrated and different levels of simulation.
- [alu_vlog] - learning HDL Bencher generate test accum
- [countqi] - Asynchrony preset counter reset the Veri
- [updowncnt] - Addition and subtraction counter, in fac
- [blocking_nonblocking] - Obstructive and non-blocking assignment
- [dispdecoder] - written in Verilog Digital Cymometer dis
- [pickup] - This is a game, through this little game
- [wenjianjiansuobaogao] - Hunan University literature class inform
- [multi16] - Verilog write the multiplier in two ways
- [OddFP] - verilog prescaler for the realization of
- [sel_key] - Automatic Identification verilog written
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Verilog--shiyanbaogao
.....................\Verilog--shiyanbaogao.doc
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