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VHDL-FPGA-Verilog
Title:
dianti_6
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Category:
VHDL-FPGA-Verilog
Tags:
File Size:
170kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
wuchunxuxu
Description:
6-storey elevator design (a detailed development process and a large amount of the Notes)
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File list
(Check if you may need any files):
dianti_6.docx
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