Description: Digital clock, which is written by VHDL, the top layer is edited by a graph, and it is completely passed through -Digital clock, using VHDL written by various modules, top-level graphics editing, in the experimental box completely through
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数字钟
......\cnt60_2.vhd
......\cont.asm.rpt
......\cont.done
......\cont.fit.rpt
......\cont.fit.summary
......\cont.flow.rpt
......\cont.map.rpt
......\cont.map.summary
......\cont.pin
......\cont.pof
......\cont.qpf
......\cont.qsf
......\cont.qws
......\cont.sim.rpt
......\cont.sof
......\cont.tan.rpt
......\cont.tan.summary
......\cont.vwf
......\db
......\..\cont.asm.qmsg
......\..\cont.cbx.xml
......\..\cont.cmp.cdb
......\..\cont.cmp.hdb
......\..\cont.cmp.logdb
......\..\cont.cmp.rdb
......\..\cont.cmp.tdb
......\..\cont.cmp0.ddb
......\..\cont.dbp
......\..\cont.db_info
......\..\cont.eco.cdb
......\..\cont.eds_overflow
......\..\cont.fit.qmsg
......\..\cont.hier_info
......\..\cont.hif
......\..\cont.map.cdb
......\..\cont.map.hdb
......\..\cont.map.logdb
......\..\cont.map.qmsg
......\..\cont.pre_map.cdb
......\..\cont.pre_map.hdb
......\..\cont.psp
......\..\cont.pss
......\..\cont.rtlv.hdb
......\..\cont.rtlv_sg.cdb
......\..\cont.rtlv_sg_swap.cdb
......\..\cont.sgdiff.cdb
......\..\cont.sgdiff.hdb
......\..\cont.sim.cvwf
......\..\cont.sim.hdb
......\..\cont.sim.qmsg
......\..\cont.sim.rdb
......\..\cont.sld_design_entry.sci
......\..\cont.sld_design_entry_dsc.sci
......\..\cont.syn_hier_info
......\..\cont.tan.qmsg
......\..\prev_cmp_cont.sim.qmsg
......\..\wed.wsf
......\prev_cmp_cont.qmsg
......\利用VHDL语言设计的数字钟.doc
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