Description: The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
- [FFT-FPGA] - 16-bit fixed-point FFT-DSP realize the F
- [AES_RTL] - Realize the use of Verilog HDL hardware
- [sha1_v01] - SHA-1 encryption algorithm of the IP cor
- [pre_norm_mul] - VHDL language used to describe a floatin
- [post_norm_addsub] - The post-normalization VHDL program sour
- [SHA1_TOP] - encryption algorithms sha_1 module, comp
- [DES] - The VHDL implement of DES encrypt algori
- [03.EDK8.2] - Xilinx virtex4 use chip design environme
File list (Check if you may need any files):
sha-1 Version1.0
................\sha-1 循环移位20080403
................\......................\sha1_2fa_slice.vhd
................\......................\sha1_32add.vhd
................\......................\sha1_3fa_slice.vhd
................\......................\sha1_4fa_nocout_slice.vhd
................\......................\sha1_4fa_slice.vhd
................\......................\sha1_add_pack.vhd
................\......................\sha1_counter.vhd
................\......................\sha1_decoder.vhd
................\......................\sha1_dff.vhd
................\......................\sha1_fa.vhd
................\......................\sha1_fa_nocout.vhd
................\......................\sha1_reg.vhd
................\......................\sha1_top.vhd
................\......................\sha1_top_tb1.vhd
................\......................\sha1_top_tb2.vhd
................\......................\sha1_wt.vhd
................\......................\说明.txt
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