Description: xilinx fpga do VGA driver signals Verilog source code, ise version 9.2,
- [Memec_3SLC_Schematic_Rev1p2] - Xilinx Spartan3 the schematics, pictures
- [USB2.0] - usb+ fpga development board schematics,
- [task_function] - I have written a verilog HDL small proce
- [lab2mb] - For the hardware design to add IP, this
- [VGA_srcfile] - VGA color display source code, has been
- [NcVerilog_tutorial] - nc verilog instructions and examples for
- [add] - Verilog hdl language commonly used adder
- [ISPDownload] - protel99 file, download cable sch and pc
- [xilinx0424] - Xilinx Chinese official training materia
- [Vga] - The code is used to interface PC monitor
File list (Check if you may need any files):
vgavga
......\device_usage_statistics.html
......\hvsync_generator.v
......\mydcm.xaw
......\my_dcm.v
......\my_dcm.xaw
......\my_dcm_arwz.ucf
......\ping.mcs
......\ping.prm
......\ping.sig
......\quadrature.v
......\timing.twr
......\vgavga.bgn
......\vgavga.bit
......\vgavga.bld
......\vgavga.cmd_log
......\vgavga.drc
......\vgavga.ipf_ISE_Backup
......\vgavga.ise
......\vgavga.ise_ISE_Backup
......\vgavga.lfp
......\vgavga.lso
......\vgavga.ncd
......\vgavga.ngc
......\vgavga.ngd
......\vgavga.ngr
......\vgavga.ntrc_log
......\vgavga.pad
......\vgavga.par
......\vgavga.pcf
......\vgavga.prj
......\vgavga.restore
......\vgavga.stx
......\vgavga.syr
......\vgavga.twr
......\vgavga.twx
......\vgavga.ucf
......\vgavga.unroutes
......\vgavga.ut
......\vgavga.v
......\vgavga.xpi
......\vgavga.xst
......\vgavga_guide.ncd
......\vgavga_map.map
......\vgavga_map.mrp
......\vgavga_map.ncd
......\vgavga_map.ngm
......\vgavga_pad.csv
......\vgavga_pad.txt
......\vgavga_prev_built.ngd
......\vgavga_summary.html
......\vgavga_summary.xml
......\vgavga_usage.xml
......\xaw2verilog.log
......\xst
......\...\dump.xst
......\...\........\vgavga.prj
......\...\........\..........\ngx
......\...\........\..........\...\notopt
......\...\........\..........\...\opt
......\...\........\..........\ntrc.scr
......\...\projnav.tmp
......\...\work
......\...\....\hdllib.ref
......\...\....\vlg2C
......\...\....\.....\vgavga.bin
......\...\....\vlg51
......\...\....\.....\hvsync__generator.bin
......\...\....\vlg7D
......\...\....\.....\my__dcm.bin
......\_impact.cmd
......\_impact.log
......\_ngo
......\....\netlist.lst
......\_pace.ucf
......\_xmsgs
......\......\bitgen.xmsgs
......\......\map.xmsgs
......\......\ngdbuild.xmsgs
......\......\par.xmsgs
......\......\trce.xmsgs
......\......\xst.xmsgs
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