arbiter Verilog prepared a bus with arbitration pr

Title: arbiter

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
3kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
baobao1008

Description: Verilog prepared a bus with arbitration proceedings. Multiple devices share the bus, the priority of different devices is changing to ensure that each device will have a fair opportunity to use the bus.

Downloaders recently: [More information of uploader baobao1008]

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File list (Check if you may need any files):

arbiter
.......\arb.v
.......\arb_fsm.v
.......\arb_tb.v
.......\counter.v
.......\monitor.v
.......\transcript
.......\xact.v

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