Description: This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM complete control module and test document, this document is to pass the test.
- [93LC46B] - EEPROM SPI interface program 93LC46
- [testbench] - An English article, a detailed descripti
- [i2cEEPROM] - Use VHDL to prepare the operation to con
- [ECCgenAndLoc] - Xilinx ISE environment based on the deve
- [USB11Core] - FPGA design USB1.1IP Core, documentation
- [ethernet_example] - FPGA to achieve the realization of Ether
File list (Check if you may need any files):
EEPROM_RD_WR
............\addr.dat
............\data.dat
............\EEPROM.cr.mti
............\eeprom.dat
............\EEPROM.mpf
............\eeprom.v
............\eeprom.v.bak
............\eeprom_wr.v
............\eeprom_wr.v.bak
............\signal
............\signal.bak
............\signal.v
............\signal.v.bak
............\top.v
............\top.v.bak
............\vsim.wlf
............\work
............\....\@e@e@p@r@o@m
............\....\............\_primary.dat
............\....\............\_primary.vhd
............\....\@e@e@p@r@o@m_@w@r
............\....\.................\_primary.dat
............\....\.................\_primary.vhd
............\....\@signal
............\....\.......\_primary.dat
............\....\.......\_primary.vhd
............\....\@top
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\_info
............\....\_opt
............\....\....\work_@e@e@p@r@o@m_@w@r_fast.asm
............\....\....\work_@e@e@p@r@o@m_@w@r_fast.dt2
............\....\....\work_@e@e@p@r@o@m_fast.asm
............\....\....\work_@e@e@p@r@o@m_fast.dt2
............\....\....\work_@signal_fast.asm
............\....\....\work_@signal_fast.dt2
............\....\....\work_@top_fast.asm
............\....\....\work_@top_fast.dt2
............\....\....\work__info
............\....\....\_deps
............\....\_opt1
............\....\.....\work_@e@e@p@r@o@m_@w@r_fast.asm
............\....\.....\work_@e@e@p@r@o@m_@w@r_fast.dt2
............\....\.....\work__info
............\....\.....\_deps
............\....\_opt2
............\....\.....\work_@e@e@p@r@o@m_@w@r_fast.asm
............\....\.....\work_@e@e@p@r@o@m_@w@r_fast.dt2
............\....\.....\work_@e@e@p@r@o@m_fast.asm
............\....\.....\work_@e@e@p@r@o@m_fast.dt2
............\....\.....\work_@signal_fast.asm
............\....\.....\work_@signal_fast.dt2
............\....\.....\work_@top_fast.asm
............\....\.....\work_@top_fast.dt2
............\....\.....\work__info
............\....\.....\_deps
............\....\_temp
Download