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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: LCD Download
 Description: LCD1602-driven FPGA-based, verilog code debugging has been successful
 Downloaders recently: [More information of uploader liangming05522]
 To Search: lcd verilog verilog LCD LCD1602 veril verilog lcd16 verilog fpga lcd veril lcd1602 veril Verilog LCD1602 lcd verilog LCD veril
  • [lcd_controller] - CFAH1602BNYAJP they simply control proce
  • [LED] - err
  • [LCD_Driver] - LCD driver with verilog HDL can be used
  • [lcd1602] - ?绦蚴迪值??| 能是 ????的16 ?? ??
  • [16X2-LCD-FPGA] - 16x2 LCD display driver design of the FP
  • [lcd-code] - Relatively complete LCD interface code,
  • [spartan_lcd] - this is an LCD verilog module
  • [lcd] - FPGA control lcd1602 (verilog)
  • [Speechrecognition] - A good voice recognition system, which c
  • [LCD1602] - 1, LCD first line: Happy 2, LCD second l
File list (Check if you may need any files): 
LCD实验
.......\Project
.......\.......\LCD_1602
.......\.......\........\component
.......\.......\........\constraint
.......\.......\........\..........\LCD_Top.pdc
.......\.......\........\coreconsole
.......\.......\........\designer
.......\.......\........\........\impl1
.......\.......\........\........\.....\designer.log
.......\.......\........\........\.....\LCD_Driver.ide_des
.......\.......\........\........\.....\LCD_Top.adb
.......\.......\........\........\.....\LCD_Top.dtf
.......\.......\........\........\.....\...........\verify.log
.......\.......\........\........\.....\LCD_Top.ide_des
.......\.......\........\........\.....\LCD_Top.pdb
.......\.......\........\........\.....\LCD_Top.pdb.depends
.......\.......\........\........\.....\LCD_Top.plk
.......\.......\........\........\.....\LCD_Top.tcl
.......\.......\........\........\.....\LCD_Top_ba.sdf
.......\.......\........\........\.....\LCD_Top_ba.v
.......\.......\........\........\.....\LCD_Top_fp
.......\.......\........\........\.....\..........\LCD_Top.log
.......\.......\........\........\.....\..........\LCD_Top.pro
.......\.......\........\........\.....\PLL_1M.ide_des
.......\.......\........\........\.....\simulation
.......\.......\........\hdl
.......\.......\........\...\Clock_Gen.v
.......\.......\........\...\LCD_Driver.v
.......\.......\........\...\LCD_Top.v
.......\.......\........\LCD_1602.prj
.......\.......\........\phy_synthesis
.......\.......\........\simulation
.......\.......\........\..........\meminit.dat
.......\.......\........\..........\modelsim.ini
.......\.......\........\..........\modelsim.ini.sav
.......\.......\........\smartgen
.......\.......\........\........\PLL_1M
.......\.......\........\........\......\PLL_1M.cxf
.......\.......\........\........\......\PLL_1M.gen
.......\.......\........\........\......\PLL_1M.log
.......\.......\........\........\......\PLL_1M.v
.......\.......\........\........\PLL_1M_work.ixf
.......\.......\........\........\smartgen.aws
.......\.......\........\stimulus
.......\.......\........\........\BtimErrors.log
.......\.......\........\........\LCD_Top.dsk
.......\.......\........\........\LCD_Top.hpj
.......\.......\........\........\waveperl.log
.......\.......\........\synthesis
.......\.......\........\.........\.recordref
.......\.......\........\.........\actgen
.......\.......\........\.........\component
.......\.......\........\.........\constraint
.......\.......\........\.........\coreconsole
.......\.......\........\.........\designer
.......\.......\........\.........\........\convert.log
.......\.......\........\.........\........\convert.tcl
.......\.......\........\.........\........\impl1
.......\.......\........\.........\........\.....\impl.prj_des
.......\.......\........\.........\........\.....\simulation
.......\.......\........\.........\........\impl2
.......\.......\........\.........\........\.....\simulation
.......\.......\........\.........\hdl
.......\.......\........\.........\LCD_Top.areasrr
.......\.......\........\.........\LCD_Top.edn
.......\.......\........\.........\LCD_Top.fse
.......\.......\........\.........\LCD_Top.htm
.......\.......\........\.........\LCD_Top.map
.......\.......\........\.........\LCD_Top.sap
.......\.......\........\.........\LCD_Top.sdf
.......\.......\........\.........\LCD_Top.srd
.......\.......\........\.........\LCD_Top.srm
.......\.......\........\.........\LCD_Top.srr
.......\.......\........\.........\LCD_Top.srs
.......\.......\........\.........\LCD_Top.tlg
.......\.......\........\.........\LCD_Top_sdc.sdc
.......\.......\........\.........\LCD_Top_syn.prj
.......\.......\........\.........\LCD_Top_syn.prj.convert.sav
.......\.......\........\.........\phy_synthesis
.......\.......\........\.........\simulation
.......\.......\........\.........\..........\modelsim.ini
.......\.......\........\.........\..........\modelsim.ini.sav
.......\.......\........\.........\smartgen
.......\.......\........\.........\stdout.log
.......\.......\........\.........\stimulus
.......\.......\........\.........\s

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