- Category:
- SCM
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[Excel]
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- 10kb
- Update:
- 2012-11-26
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Description: DA algorithm used in the lookup table module, the design of the program first look-up table, and then design 4* 4DA algorithm module, after the word-bit expansion and extension of the procedure to be 32-order filter
- [Foundation_Chinese] - Xilinx complete directory foundation
- [DDS_Power] - FPGA on the verilog language programming
- [VHDL_FIR11] - using VHDL search forms for the FIR filt
- [DDS] - In FPGA-based lookup table approach (LUT
- [FIR_verilog] - Verilog based on the FIR filter, there a
- [Mean_64] - Original code, the use of VHDL to achiev
- [16_FIR] - 16-order FIR filter - this design USES t
- [cic512] - 5-order CIC filter, collected 12 times t
- [ImplementLUT-baseFIRFilterwithVHDL] - VHDL language used lookup table method t
- [FPGA_LUT] - Large-scale look-up table-based FPGA des
File list (Check if you may need any files):
case1.vhd
case2.vhd
case3.vhd
case4.vhd
滤波器序数.xls
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