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VHDL-FPGA-Verilog
Title:
fifo8
Download
Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
fangchunen
Description:
FIFO source, verilog HDL to achieve their own verified, no problem
Downloaders recently:
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More information of uploader fangchunen
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To Search:
fifo verilog
Verilog
Verilog FIFO
[
uart-verilog-vhdl
] - with vhdl and verilog prepared by the se
[
verilog.HDL.examples
] - many very useful Verilog examples : ADC,
[
FIFO_Buffer
] - Synchronous and asynchronous sequential
[
fifo
] - A First in first out buffer in Verilog
[
fifo
] - a_fifo5.v verilog code for asynchronous
[
fifo-verilog
] - Own design of a FIFO register, with veri
File list
(Check if you may need any files):
fifo8.v
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