Title:
A_bit_serial_data_transmitter
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Description: • To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter.
• To verify the correct behaviour of each component part by means of simulation.
• To construct a top-level module corresponding to the Asynchronous Serial Data Transmitter, making use of the component parts developed above, and any additional behavioural elements which may be required.
• To verify the correct operation of the top-level design by means of simulation using a Verilog-HDL test-fixture.
• To automatically create a hierarchical logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool.
File list (Check if you may need any files):
A bit serial data transmitter
.............................\test_txsystem.v
.............................\txsys.ucf
.............................\txsys.v
