Description: Synchronous digital multiplex design and its FPGA implementation
The brief introduction of the basic principle of synchronous digital multiple connection, on the basis of using VHDL language to synchronous digital multiplex has carried on the design of each module, and under the environment of ISE integrated the design description, integration, layout in time sequence simulation, obtained as a result, the correct design and use of medium and small capacity of FPGA to realize the function of synchronous digital multiplex.
Base rate digital signal synthesis equipment and tapping equipment is the key equipment used in telecom network is more, in the user module of digital program-controlled switches, PHS base station controller and group the phone you need to use this kind of synchronous digital multiplex equipment. In recent years, with the increasing number of companies and enterprises requiring self-built internal communication systems, the use of synchronous digital multiplex equipment has also increased. The high performance of FPGA (field programmable gate array) devices simplifies the design and implementation of digital communication systems. Based on the technical features of FPGA and the basic principle of digital multiplex technology, the digital subdivision and reconnection of base group speed (2048kbps) digital signal are realized.
- VHDL
File list (Check if you may need any files):
myprojects
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