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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: UpDownCounter Download
 Description: an up down counter in verilog
 To Search: counter verilog
File list (Check if you may need any files):
bistabil.v


counterPart1.v
counterPart2.v
counterPart3.v
counterPorti.v
counterPorti_tb.v
counterPorti_test.v
DW03_bictr_dcnto.pdf
mux21.v



pozna4.JPG
schema synplify.JPG
sumator1bit.v
sumator1bitNoCarryIn.v
sumator1bitNoCarryOut.v
test.v
transcript
UDCounter.v
UDCounter_tb.v
UDCounter_test.v
    

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