BancRegistre.vhdl
Flag.vhdl
Flag.vhdl.bak
lesTestsBench





.............\RI4.bmp
.............\RI5.bmp
.............\RI6.bmp
.............\RI7.bmp
.............\Thumbs.db
RI.vhdl
RI.vhdl.bak
TestBenchBancRegister.vhdl
TestBenchRegFlag.vhdl
TestBenchRi.vhdl
TestBenchRi.vhdl.bak
transcript
vsim.wlf
work
....\instr_reg
....\.........\behave.dat
....\.........\_primary.dat
....\instr_reg_test
....\..............\arch.dat
....\..............\_primary.dat
....\ri
....\..\behave.dat
....\..\_primary.dat
....\_info
....\_opt
....\....\work_instr_reg_test_arch.asm
....\....\work__info
....\....\_deps
....\....\__model_tech_.._ieee__info
....\....\__model_tech_.._std__info
....\_opt1
....\.....\work_instr_reg_behave.asm
....\.....\work__info
....\.....\_deps
....\.....\__model_tech_.._ieee__info
....\.....\__model_tech_.._std__info
....\_temp