Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: homework32 Download
 Description: This is a 32-bit shift register, is prepared verilog, can be realized from the 1-31 shift left or right
 Downloaders recently: [More information of uploader 704897786]
 To Search:
  • [verilog] - The realization of some of the basic dev
File list (Check if you may need any files): 
homework32.v

CodeBus www.codebus.net