Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: xapp860 Download
 Description: 16-Channel, DDR LVDS Interface with Real-Time Window Monitoring
 Downloaders recently: [More information of uploader wicky.zhang]
  • [VBuffer_1c6] - Video Capture SDRAM and latches to the i
  • [lvds_tx_rx_ok] - Nios system
  • [diff_io_top] - LVDS Application of Verilog HDL examples
  • [alteralvds] - Series altera-based chip interface lvds
  • [CODE] - ddr2 source code ddr 2 source code
  • [ddr2] - Xilinx fpga-based controller design meth
  • [ddr_sdr_V1_1] - DR SDRAM Controller Core - has been desi
File list (Check if you may need any files):
readme.txt
VERILOG
.......\BIT_ALIGN_MACHINE.v
.......\DDR_6TO1_16CHAN_RT_RX.v
.......\DDR_6TO1_16CHAN_RT_TX.v
.......\RESOURCE_SHARING_CONTROL.v
.......\RT_WINDOW_MONITOR.v
VHDL
....\BIT_ALIGN_MACHINE.vhd
....\count_to_128.vhd
....\count_to_16x.vhd
....\COUNT_TO_64.vhd
....\DDR_6TO1_16CHAN_RT_RX.vhd
....\DDR_6TO1_16CHAN_RT_TX.vhd
....\RESOURCE_SHARING_CONTROL.vhd
....\RT_WINDOW_MONITOR.vhd
....\seven_bit_reg_w_ce.vhd
xapp860.pdf
    

CodeBus www.codebus.net