Description: SDRAM control of the most complete IP core, including source code, simulation, as well as IP core description files, it can be helpful
- [tftlcd] - TFT LCD controller verilog code using AL
- [vhdl-MIPS] - Quartus-Altera Nios... VHDl based, compl
- [8051IP] - mc8051 IP Core source code available for
- [image_control] - NIOSII read through the IP core in CMOS
File list (Check if you may need any files):
sdr sdram controller
....................\sdr_sdram.pdf
....................\verilog
....................\.......\doc
....................\.......\...\readme.txt
....................\.......\...\sdr_sdram.pdf
....................\.......\model
....................\.......\.....\mt48lc8m16a2.v
....................\.......\route
....................\.......\.....\PLL1.v
....................\.......\.....\sdr_sdram.csf
....................\.......\.....\sdr_sdram.esf
....................\.......\.....\sdr_sdram.vqm
....................\.......\simulation
....................\.......\..........\modelsim.ini
....................\.......\..........\readme.txt
....................\.......\..........\sdr_sdram_tb.v
....................\.......\..........\work
....................\.......\..........\....\altclklock
....................\.......\..........\....\..........\verilog.psm
....................\.......\..........\....\..........\_primary.dat
....................\.......\..........\....\..........\_primary.vhd
....................\.......\..........\....\command
....................\.......\..........\....\.......\verilog.psm
....................\.......\..........\....\.......\_primary.dat
....................\.......\..........\....\.......\_primary.vhd
....................\.......\..........\....\control_interface
....................\.......\..........\....\.................\verilog.psm
....................\.......\..........\....\.................\_primary.dat
....................\.......\..........\....\.................\_primary.vhd
....................\.......\..........\....\mt48lc8m16a2
....................\.......\..........\....\............\verilog.psm
....................\.......\..........\....\............\_primary.dat
....................\.......\..........\....\............\_primary.vhd
....................\.......\..........\....\pll1
....................\.......\..........\....\....\verilog.psm
....................\.......\..........\....\....\_primary.dat
....................\.......\..........\....\....\_primary.vhd
....................\.......\..........\....\sdr_data_path
....................\.......\..........\....\.............\verilog.psm
....................\.......\..........\....\.............\_primary.dat
....................\.......\..........\....\.............\_primary.vhd
....................\.......\..........\....\sdr_sdram
....................\.......\..........\....\.........\verilog.psm
....................\.......\..........\....\.........\_primary.dat
....................\.......\..........\....\.........\_primary.vhd
....................\.......\..........\....\sdr_sdram_tb
....................\.......\..........\....\............\verilog.psm
....................\.......\..........\....\............\_primary.dat
....................\.......\..........\....\............\_primary.vhd
....................\.......\..........\....\_info
....................\.......\source
....................\.......\......\altclklock.v
....................\.......\......\Command.v
....................\.......\......\compile_all.v
....................\.......\......\control_interface.v
....................\.......\......\Params.v
....................\.......\......\PLL1.v
....................\.......\......\sdr_data_path.v
....................\.......\......\sdr_sdram.v
....................\.......\synthesis
....................\.......\.........\synplicity
....................\.......\.........\..........\sdr_sdram.prj
....................\vhdl
....................\....\doc
....................\....\...\readme.txt
....................\....\...\sdr_sdram.pdf
....................\....\model
....................\....\.....\io_utils.vhd
....................\....\.....\mt48lc8m16a2.vhd
....................\....\.....\mt48lc8m16a2.zip
....................\....\.....\mti_pkg.vhd
....................\....\.....\stdlogar.vhd
....................\....\.....\util1164.vhd
....................\....\route
....................\....\.....\pll1.vhd
....................\....\.....\sdr_sdram.csf
....................\...
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