Description: With VHDL language design 8 accumulators: in eight accumulator codes in one: The accumulator is 8 accumulator logic circuit which is composed of two 4 binary system accumulator U1 and U2, U1 uses for to load in 8 accumulators two addend low 4, but U2 uses for to load high 4. When designs 4 accumulators, the definition input signal measures CIN, A, B as well as the output signal measures S, Cout. The definition signal measures SINT/AA/BB, after addend A and 0 juxtapositions, bestows on for AA, after addend B and 0 juxtapositions, bestows on for BB, forms 5 binary system number, this is for when does the addition has processing which the overflow does, then as well as carries Cin addend AA and BB to levy additional taxes for SINT, and the SINT low 4 taxes for the addend and the S output, simultaneously transmits the SINT highest order to the Cout output. When designs 8 accumulators, defines a signal to measure CARRY, bestows on 4 accumulator U1 COUT for CARRY, bestows on again the CARRY
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.....\八位加法器源代码1.doc
.....\八位加法器源代码2.doc
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