Description: Modelsim beginners to learn a good example of Verilog based on the counter, with the test source code, running in quartus2.
File list (Check if you may need any files):
counter
.......\counter.asm.rpt
.......\counter.done
.......\counter.eda.rpt
.......\counter.fit.rpt
.......\counter.fit.smsg
.......\counter.fit.summary
.......\counter.flow.rpt
.......\counter.map.rpt
.......\counter.map.summary
.......\counter.pin
.......\counter.pof
.......\counter.qpf
.......\counter.qsf
.......\counter.qws
.......\counter.sof
.......\counter.tan.rpt
.......\counter.tan.summary
.......\counter.v
.......\counter_nativelink_simulation.rpt
.......\counter_tb.v
.......\db
.......\..\counter.asm.qmsg
.......\..\counter.cbx.xml
.......\..\counter.cmp.bpm
.......\..\counter.cmp.cdb
.......\..\counter.cmp.ecobp
.......\..\counter.cmp.hdb
.......\..\counter.cmp.kpt
.......\..\counter.cmp.logdb
.......\..\counter.cmp.rdb
.......\..\counter.cmp.tdb
.......\..\counter.cmp0.ddb
.......\..\counter.cmp_merge.kpt
.......\..\counter.db_info
.......\..\counter.eco.cdb
.......\..\counter.eda.qmsg
.......\..\counter.fit.qmsg
.......\..\counter.hier_info
.......\..\counter.hif
.......\..\counter.map.bpm
.......\..\counter.map.cdb
.......\..\counter.map.ecobp
.......\..\counter.map.hdb
.......\..\counter.map.kpt
.......\..\counter.map.logdb
.......\..\counter.map.qmsg
.......\..\counter.map_bb.cdb
.......\..\counter.map_bb.hdb
.......\..\counter.map_bb.hdbx
.......\..\counter.map_bb.logdb
.......\..\counter.pre_map.cdb
.......\..\counter.pre_map.hdb
.......\..\counter.psp
.......\..\counter.rtlv.hdb
.......\..\counter.rtlv_sg.cdb
.......\..\counter.rtlv_sg_swap.cdb
.......\..\counter.sgdiff.cdb
.......\..\counter.sgdiff.hdb
.......\..\counter.sld_design_entry.sci
.......\..\counter.sld_design_entry_dsc.sci
.......\..\counter.syn_hier_info
.......\..\counter.tan.qmsg
.......\..\counter.tis_db_list.ddb
.......\..\counter.tmw_info
.......\..\prev_cmp_counter.asm.qmsg
.......\..\prev_cmp_counter.eda.qmsg
.......\..\prev_cmp_counter.fit.qmsg
.......\..\prev_cmp_counter.map.qmsg
.......\..\prev_cmp_counter.qmsg
.......\..\prev_cmp_counter.tan.qmsg
.......\incremental_db
.......\..............\compiled_partitions
.......\..............\...................\counter.root_partition.cmp.atm
.......\..............\...................\counter.root_partition.cmp.dfp
.......\..............\...................\counter.root_partition.cmp.hdbx
.......\..............\...................\counter.root_partition.cmp.kpt
.......\..............\...................\counter.root_partition.cmp.logdb
.......\..............\...................\counter.root_partition.cmp.rcf
.......\..............\...................\counter.root_partition.map.atm
.......\..............\...................\counter.root_partition.map.dpi
.......\..............\...................\counter.root_partition.map.hdbx
.......\..............\...................\counter.root_partition.map.kpt
.......\..............\README
.......\simulation
.......\..........\modelsim
.......\..........\........\counter.sft
.......\..........\........\counter.vo
.......\..........\........\counter_modelsim.xrf
.......\..........\........\counter_run_msim_gate_verilog.do
.......\..........\........\counter_run_msim_gate_verilog.do.bak1
.......\..........\........\counter_run_msim_gate_verilog.do.bak2
.......\..........\........\counter_run_msim_gate_verilog.do.bak3
.......\..........\........\counter_run_msim_gate_verilog.do.bak4
.......\..........\........\counter_run_msim_gate_verilog.do.bak5
.......\..........\........\counter_run_msim_rtl_verilog.do
.......\..........\........\counter_run_msim_rtl_verilog.do.bak1
.......\..........\........\counter_run_msim_rtl_verilog.do.bak2
.......\..........\........\counter_run_msim_rtl_verilog.do.bak3
.......\..........\........\counter_run_msim_rtl_verilog.do.bak4