Description: Altra as quartus8.1 use the development environment, language VHDL hardware changes to achieve the fft
- [SDRAMcontrollor] - SDRAM controller, the following is my SD
- [pll] - VERILOG language with the digital phase-
File list (Check if you may need any files):
fft——VHDL
...........\fft5
...........\....\and_gates.vhd
...........\....\and_gates.vhd.bak
...........\....\baseindex.vhd
...........\....\baseindex.vhd.bak
...........\....\but.vhd
...........\....\but.vhd.bak
...........\....\butter_lib.vhd
...........\....\comm.txt
...........\....\control2.vhd
...........\....\control2.vhd.bak
...........\....\controller.vhd
...........\....\controller.vhd.bak
...........\....\counter.vhd
...........\....\counter.vhd.bak
...........\....\cycles_but.vhd
...........\....\cycles_but.vhd.bak
...........\....\db
...........\....\..\fft5.db_info
...........\....\..\fft5.eco.cdb
...........\....\..\fft5.sld_design_entry.sci
...........\....\..\prev_cmp_fft5.map.qmsg
...........\....\..\prev_cmp_fft5.qmsg
...........\....\dff.vhd
...........\....\dff.vhd.bak
...........\....\divide.vhd
...........\....\divide.vhd.bak
...........\....\fft5.flow.rpt
...........\....\fft5.map.rpt
...........\....\fft5.map.summary
...........\....\fft5.qpf
...........\....\fft5.qsf
...........\....\fft5.qws
...........\....\FLOAT2.PIF
...........\....\FLOAT_RE.TXT
...........\....\IEEE_TO_.PIF
...........\....\incremental_db
...........\....\..............\compiled_partitions
...........\....\..............\README
...........\....\ioadd.vhd
...........\....\ioadd.vhd.bak
...........\....\iod_staged.vhd
...........\....\iod_staged.vhd.bak
...........\....\lblock.vhd
...........\....\lblock.vhd.bak
...........\....\mult.vhd
...........\....\mult.vhd.bak
...........\....\multiply.vhd
...........\....\multiply.vhd.bak
...........\....\mux_add.vhd
...........\....\mux_add.vhd.bak
...........\....\mux_but.vhd
...........\....\mux_but.vhd.bak
...........\....\negate.vhd
...........\....\negate.vhd.bak
...........\....\normalize.vhd
...........\....\normalize.vhd.bak
...........\....\out_result.vhd
...........\....\out_result.vhd.bak
...........\....\print.vhd
...........\....\print.vhd.bak
...........\....\ram.vhd
...........\....\ram.vhd.bak
...........\....\ram_shift.vhd
...........\....\ram_shift.vhd.bak
...........\....\rblock.vhd
...........\....\rblock.vhd.bak
...........\....\result.txt
...........\....\rom.vhd
...........\....\rom.vhd.bak
...........\....\romadd_gen.vhd
...........\....\romadd_gen.vhd.bak
...........\....\rom_ram.vhd
...........\....\rom_ram.vhd.bak
...........\....\shift2.vhd
...........\....\shift2.vhd.bak
...........\....\simili.lst
...........\....\stage.vhd
...........\....\stage.vhd.bak
...........\....\subtractor.vhd
...........\....\subtractor.vhd.bak
...........\....\summer.vhd
...........\....\summer.vhd.bak
...........\....\swap.vhd
...........\....\swap.vhd.bak
...........\....\synth_main.vhd
...........\....\synth_main.vhd.bak
...........\....\synth_test.vhd
...........\....\synth_test.vhd.bak
...........\....\新建文件夹
...........\....\..........\control2.vhd
...........\....\..........\normalize.vhd
...........\....\..........\shift2.vhd
...........\....\..........\subtractor.vhd
...........\....\..........\summer.vhd
...........\....\..........\swap.vhd