Description: ISE using the core generator to generate the memory interface design (MIG), including the example design and user design
- [ddr] - ISE MIG1.6 generated DDR SDRAM controlle
- [ddr_ctrl] - verilog hdl coding DDR sdram control for
- [ISE_chinese_user_guide] - Xilinx - ISE's Chinese instructions are
- [testbench] - This how to prepare Testbench, I think i
- [mig007] - XILINX memory interface generator.
- [TXT2UCF] - The software for the schematic diagram o
- [FPGA_test] - Question of the FPGA pen name of enterpr
- [DDR_Xilinx] - xilinx公司DDR控制ip
- [mgc_licen(1)] - license for ise12.2，It s lastest fot ise
File list (Check if you may need any files):
mig_23
......\example_design
......\..............\datasheet.txt
......\..............\log.txt
......\..............\mig.prj
......\..............\par
......\..............\...\compatible_ucf
......\..............\...\..............\xc3s400a_fg400.ucf
......\..............\...\create_ise.bat
......\..............\...\icon_coregen.xco
......\..............\...\ila_coregen.xco
......\..............\...\ise_flow.bat
......\..............\...\ise_run.txt
......\..............\...\mem_interface_top.ut
......\..............\...\mig_23.ucf
......\..............\...\readme.txt
......\..............\...\set_ise_prop.txt
......\..............\...\vio_coregen.xco
......\..............\rtl
......\..............\...\mig_23.v
......\..............\...\mig_23_addr_gen_0.v
......\..............\...\mig_23_cal_ctl.v
......\..............\...\mig_23_cal_top.v
......\..............\...\mig_23_clk_dcm.v
......\..............\...\mig_23_cmd_fsm_0.v
......\..............\...\mig_23_cmp_data_0.v
......\..............\...\mig_23_controller_0.v
......\..............\...\mig_23_controller_iobs_0.v
......\..............\...\mig_23_data_gen_0.v
......\..............\...\mig_23_data_path_0.v
......\..............\...\mig_23_data_path_iobs_0.v
......\..............\...\mig_23_data_read_0.v
......\..............\...\mig_23_data_read_controller_0.v
......\..............\...\mig_23_data_write_0.v
......\..............\...\mig_23_dqs_delay.v
......\..............\...\mig_23_fifo_0_wr_en_0.v
......\..............\...\mig_23_fifo_1_wr_en_0.v
......\..............\...\mig_23_infrastructure.v
......\..............\...\mig_23_infrastructure_iobs_0.v
......\..............\...\mig_23_infrastructure_top.v
......\..............\...\mig_23_iobs_0.v
......\..............\...\mig_23_main_0.v
......\..............\...\mig_23_parameters_0.v
......\..............\...\mig_23_ram8d_0.v
......\..............\...\mig_23_rd_gray_cntr.v
......\..............\...\mig_23_s3_dm_iob.v
......\..............\...\mig_23_s3_dqs_iob.v
......\..............\...\mig_23_s3_dq_iob.v
......\..............\...\mig_23_tap_dly.v
......\..............\...\mig_23_test_bench_0.v
......\..............\...\mig_23_top_0.v
......\..............\...\mig_23_wr_gray_cntr.v
......\..............\sim
......\..............\...\ddr2_model.v
......\..............\...\ddr2_model_parameters.vh
......\..............\...\glbl.v
......\..............\...\sim.do
......\..............\...\sim.exe
......\..............\...\simulation_help.chm
......\..............\...\sim_tb_top.v
......\..............\...\transcript
......\..............\...\wiredly.v
......\..............\synth
......\..............\.....\mem_interface_top_synp.sdc
......\..............\.....\mig_23.lso
......\..............\.....\mig_23.prj
......\..............\.....\script_synp.tcl
......\user_design
......\...........\datasheet.txt
......\...........\log.txt
......\...........\mig.prj
......\...........\par
......\...........\...\compatible_ucf
......\...........\...\..............\xc3s400a_fg400.ucf
......\...........\...\create_ise.bat
......\...........\...\icon_coregen.xco
......\...........\...\ila_coregen.xco
......\...........\...\ise_flow.bat
......\...........\...\ise_run.txt
......\...........\...\mem_interface_top.ut
......\...........\...\mig_23.ucf
......\...........\...\readme.txt
......\...........\...\set_ise_prop.txt
......\...........\...\vio_coregen.xco
......\...........\rtl
......\...........\...\mig_23.v
......\...........\...\mig_23_cal_ctl.v
......\...........\...\mig_23_cal_top.v
......\...........\...\mig_23_clk_dcm.v
......\...........\...\mig_23_controller_0.v
......\...........\...\mig_23_controller_iobs_0.v
......\...........\...\mig_23_data_path_0.v
......\...........\...\mig_23_data_path_iobs_0.v
......\...........\...\mig_23_data_read_0.v
......\...........\...\mig_23_data_read_controller_0.v
......\...........\...\mig_23_data_write_0.v
......\...........\...\mig_23_dqs_delay.v
......\...........\...\mig_23_fifo_0_wr_en_0.v
......\...........\...\mig_23_fifo_1_wr_en_0.v
......\...........\...\mig_23_infrastru
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