Description: dds, FPGA waveform generator, wave form, to receive, send
- [FPGA+DSS+UART] - Using FPGA to achieve arbitrary waveform
- [sine] - Verilog programming, the use of FPGA rea
- [dds_good] - The use of DDS technology waveform gener
- [EPM3128ATC100-Pins] - This tutorial matching CT-SOPCx series F
- [DDSsinROMsample] - fpga DDS ROM sinusoidal waveform is a ha
- [dds] - Using DDS technology, the use of FPGA ch
- [DDS-FPGA] - FPGA-based DDS information!
- [DDS-FM-FPGA] - DDS introduced, FM Signal Generator! FM
File list (Check if you may need any files):
信号源双路（组合版）
....................\add.bsf
....................\add.v
....................\add2.bsf
....................\add2.v
....................\add2_bb.v
....................\add_bb.v
....................\AorB.bsf
....................\AorB.v
....................\db
....................\..\add_sub_2fg.tdf
....................\..\add_sub_3fg.tdf
....................\..\add_sub_4tg.tdf
....................\..\add_sub_5tg.tdf
....................\..\add_sub_nig.tdf
....................\..\altsyncram_lu21.tdf
....................\..\dds.analyze_file.qmsg
....................\..\dds.asm.qmsg
....................\..\dds.cbx.xml
....................\..\dds.cmp.cdb
....................\..\dds.cmp.hdb
....................\..\dds.cmp.kpt
....................\..\dds.cmp.logdb
....................\..\dds.cmp.rdb
....................\..\dds.cmp.tdb
....................\..\dds.cmp0.ddb
....................\..\dds.dbp
....................\..\dds.db_info
....................\..\dds.eco.cdb
....................\..\dds.eds_overflow
....................\..\dds.fit.qmsg
....................\..\dds.hier_info
....................\..\dds.hif
....................\..\dds.map.cdb
....................\..\dds.map.hdb
....................\..\dds.map.logdb
....................\..\dds.map.qmsg
....................\..\dds.pre_map.cdb
....................\..\dds.pre_map.hdb
....................\..\dds.psp
....................\..\dds.rtlv.hdb
....................\..\dds.rtlv_sg.cdb
....................\..\dds.rtlv_sg_swap.cdb
....................\..\dds.sgdiff.cdb
....................\..\dds.sgdiff.hdb
....................\..\dds.signalprobe.cdb
....................\..\dds.sim.hdb
....................\..\dds.sim.qmsg
....................\..\dds.sim.rdb
....................\..\dds.sim.vwf
....................\..\dds.sld_design_entry.sci
....................\..\dds.sld_design_entry_dsc.sci
....................\..\dds.smp_dump.txt
....................\..\dds.syn_hier_info
....................\..\dds.tan.qmsg
....................\..\wed.zsf
....................\dds.asm.rpt
....................\dds.bdf
....................\dds.cdf
....................\dds.done
....................\dds.dpf
....................\dds.fit.rpt
....................\dds.fit.smsg
....................\dds.fit.summary
....................\dds.flow.rpt
....................\dds.map.rpt
....................\dds.map.smsg
....................\dds.map.summary
....................\dds.pin
....................\dds.pof
....................\dds.qpf
....................\dds.qsf
....................\dds.qws
....................\dds.sim.rpt
....................\dds.sof
....................\dds.tan.rpt
....................\dds.tan.summary
....................\dds.vwf
....................\f5mhz.bsf
....................\f5mhz.v
....................\high10.bsf
....................\high10.v
....................\receive_f.bsf
....................\receive_f.v
....................\receive_X.bsf
....................\receive_X.v
....................\sine.mif
....................\sine_rome.bsf
....................\sine_rome.v
....................\sine_rome_bb.v
....................\sine_room2.bsf
....................\sine_room2.v
....................\sine_room2_bb.v
....................\sopc_builder_debug_log.txt
....................\xiangyi.bsf
....................\xiangyi.v
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