Description: The CPLD-based PWM waveform generator, the programming language to verilog, development environment for QuartusII.
- [SVPWM] - This is a motor SVPWM Speed VHDL source
- [dspCode] - PWM waveform generator, for example, TMS
- [motor_PWM_Verilog] - DC motor verilog hdl code, suitable for
- [SPWM] - Cpld developed by spwm waves on the gene
- [PWM_moto_ctrl] - verilog code for PWM DC motor control to
- [pwm] - PWM pulse generation code, the program u
- [spwm] - SPWM modulation on the design of VHDL co
File list (Check if you may need any files):
transfer.v