Description: Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations.
- [mips_creative] - a complete MIPS CPU, innovative design,
- [fir_filter] - regular FIR filter coefficients of VHDL
- [DuZheDL] - directly to the extension changed. Pas c
- [riscpu] - a 32 Microprocessor verilog achieve puls
- [cmult] - Complex Multiplier FPGA to achieve, and
- [multiply2] - 18bit multipliers used booth2 the booth
- [wallace] - This is a code for wallace tree multipli
- [cmultip] - With VERILOG HDL achieve savings of 16-b
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期刊论文
........\一种基于FPGA实现的FFT结构.pdf
........\使用说明请参看右侧注释====〉〉.txt
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