i2c FPGA implementation of the I2C bus, the source

Title: i2c

Category:
VHDL-FPGA-Verilog
Tags:
[ASM] [源码]
File Size:
2.26mb
Update:
2012-11-26
Downloads:
1 Times
Uploaded by:
saind_xiao

Description: FPGA implementation of the I2C bus, the source code, debugging is passed, I have used it for few years .

Downloaders recently: [More information of uploader saind_xiao]

To Search: fpga i2c I2C FPGA FPGA

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File list (Check if you may need any files):

i2c
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...\.....\CVS
...\.....\...\Entries
...\.....\...\Repository
...\.....\...\Root
...\.....\verilog
...\.....\.......\CVS
...\.....\.......\...\Entries
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...\.....\.......\...\Root
...\.....\.......\i2c_slave_model.v
...\.....\.......\i2c_slave_model.v.bak
...\.....\.......\spi_slave_model.v
...\.....\.......\spi_slave_model.v.bak
...\.....\.......\tst_bench_top.v
...\.....\.......\tst_bench_top.v.bak
...\.....\.......\wb_master_model.v
...\.....\.......\wb_master_model.v.bak
...\CVS
...\...\Entries
...\...\Repository
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...\doc
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...\...\i2c_specs.pdf
...\...\src
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...\...\...\I2C_specs.doc
...\rtl
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...\...\verilog
...\...\.......\CVS
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...\...\.......\...\Root
...\...\.......\i2c_master_bit_ctrl.v
...\...\.......\i2c_master_bit_ctrl.v.bak
...\...\.......\i2c_master_byte_ctrl.v
...\...\.......\i2c_master_byte_ctrl.v.bak
...\...\.......\i2c_master_defines.v
...\...\.......\i2c_master_top.v
...\...\.......\i2c_master_top.v.bak
...\...\.......\timescale.v
...\...\vhdl
...\...\....\CVS
...\...\....\...\Entries
...\...\....\...\Repository
...\...\....\...\Root
...\...\....\I2C.VHD
...\...\....\i2c_master_bit_ctrl.vhd
...\...\....\i2c_master_byte_ctrl.vhd
...\...\....\i2c_master_top.vhd
...\...\....\readme
...\...\....\tst_ds1621.vhd
...\sim
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\i2c.cr.mti
...\...\i2c.mpf
...\...\i2c_verilog
...\...\...........\CVS
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...\...\...........\run
...\...\...........\...\bench.vcd
...\...\...........\...\CVS
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...\...\...........\...\INCA_libs
...\...\...........\...\.........\CVS
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...\...\...........\...\ncverilog.key
...\...\...........\...\ncverilog.log
...\...\...........\...\run
...\...\...........\...\waves
...\...\...........\...\.....\CVS
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...\...\vsim.wlf
...\...\work
...\...\....\@m@a@x@i@i_@p@r@i@m_@d@f@f@e
...\...\....\............................\verilog.asm
...\...\....\............................\_primary.dat

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