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Title: DPLL Download
 Description: pll digital impliment
  • [verilogpll] - using Verilog language prepared by the D
  • [SAT4J_JAVA] - Java version of the SAT solver, based on
  • [clkrecoveryDPLL] - Clock recovery for all-digital phase-loc
  • [pll] - Using FPGA digital phase-locked loop, de
  • [006] - Based on the FPGA realization of a new d
  • [dpll] - The basic principles of phase-locked loo
  • [EP2C8_pll_example] - EP2C8 PLL cases of the examples to those
  • [PLL] - Matlab with VHDL and digital phase-locke
  • [sat] - satisfiability problem(SAT) MPI,NP PROBL
  • [DPLL] - Digital phase loop lock design with veri
File list (Check if you may need any files):
DPLL
....\dff.v
....\dff.v.bak
....\divider_2.v
....\divider_2.v.bak
....\divider_n.v
....\divider_n.v.bak
....\DLL
....\...\@d@p@l@l_@t@e@s@t
....\...\.................\verilog.asm
....\...\.................\_primary.dat
....\...\.................\_primary.vhd
....\...\andx
....\...\....\verilog.asm
....\...\....\_primary.dat
....\...\....\_primary.vhd
....\...\dff
....\...\...\verilog.asm
....\...\...\_primary.dat
....\...\...\_primary.vhd
....\...\divider_2
....\...\.........\verilog.asm
....\...\.........\_primary.dat
....\...\.........\_primary.vhd
....\...\divider_n
....\...\.........\verilog.asm
....\...\.........\_primary.dat
....\...\.........\_primary.vhd
....\...\kcounter
....\...\........\verilog.asm
....\...\........\_primary.dat
....\...\........\_primary.vhd
....\...\_info
....\DLL.cr.mti
....\DLL.mpf
....\DLL_TEST.v
....\DLL_TEST.v.bak
....\DPLL
....\....\_info
....\DPLL.cr.mti
....\DPLL.mpf
....\kcounter.v
....\kcounter.v.bak
....\transcript
....\vsim.wlf
....\xor.v
....\xor.v.bak
    

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