Description: VHDL compiled CPLD sine wave generation process by direct numerical synthesis of theory-driven dac0832 achieved DDS sine wave input
To Search:
- [eda] - Application of FPGA, a sinusoidal signal
- [2ask] - Modulation and demodulation 2ask top-lev
- [sin] - Quartus II 5.0 on the preparation of the
- [example10] - : Sine wave generator routine, including
- [DDS] - Produced with the DDS sine wave 3MHZ.
- [DDS] - DDS WRITE IN VHDL ,including FSK ASK
File list (Check if you may need any files):
dds.vhd