rrc_filter this is a verilog code for root raised - CodeBus

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VHDL-FPGA-Verilog

Title: rrc_filter

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
1kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
vlsi.006

Description: this is a verilog code for root raised cosine filter

Downloaders recently: [More information of uploader vlsi.006]

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rrc_filter.v

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